Output Impedance of a Voltage Source

Experiment: Output Impedance of a Voltage Source

1. Aim

To demonstrate the concept of output impedance of a practical voltage source using the programmable DC source PV1 of SEELab3, and to determine the voltage at which the actual output begins to deviate from the set-point due to the finite output impedance of the source.

2. Apparatus / Components Required

• SEELab3 unit
• Resistor $R_L = 100\text{ }\Omega$ (load resistor)
• Connecting wires
• PC or Smartphone with SEELab3 software

3. Theory & Principle

3.1 Ideal vs Practical Voltage Source

An ideal voltage source maintains a perfectly constant terminal voltage regardless of the current drawn from it. Its output impedance is zero.

A practical voltage source, however, has a finite internal (output) impedance $Z_{out}$ in series with the ideal source. This can be modelled as:

where $V_{set}$ is the no-load (open-circuit) set-point voltage, $I$ is the load current, and $Z_{out}$ is the output impedance. The terminal voltage $V_{terminal}$ is what actually appears at the output terminals and is always less than $V_{set}$ whenever current is drawn.

3.2 Voltage Divider Effect

When a load resistor $R_L$ is connected, the circuit forms a voltage divider between $Z_{out}$ and $R_L$:

The fractional voltage drop across $Z_{out}$ is:

For $Z_{out} \ll R_L$ this drop is negligible and the source behaves nearly ideally. As $V_{set}$ is increased, the current $I = V_{terminal}/R_L$ increases, and the drop $I \cdot Z_{out}$ grows until the source can no longer sustain the set-point — the terminal voltage saturates.

3.3 Determining $Z_{out}$

By measuring the open-circuit voltage $V_{OC}$ (no load, $R_L = \infty$) and the loaded terminal voltage $V_L$ with a known load $R_L$, the output impedance can be calculated as:

Alternatively, from the slope of the $V_{terminal}$ vs $I$ graph:

A steeper slope indicates a higher output impedance (a “weaker” source).

3.4 Current Limit and Saturation

Every practical source has a maximum current it can deliver, set by either the output impedance or an internal current-limiting circuit. Beyond the saturation point, increasing $V_{set}$ no longer raises the terminal voltage proportionally — the $V_{terminal}$ vs $V_{set}$ curve bends away from the ideal $45°$ line.

4. Circuit Diagram / Setup

1. Connect one end of the load resistor $R_L$ ($100\text{ }\Omega$) to PV1 (Programmable Voltage output).
2. Connect the other end of $R_L$ to GND.
3. Connect PV1 also to A1 to monitor the actual terminal voltage of the source.

The measured voltage at A1 is the true terminal voltage — it includes the effect of output impedance. The set-point is what you program in the software. Comparing the two reveals the voltage drop across $Z_{out}$.

5. Procedure

1. Open the SEELab3 app and navigate to the “Output Impedance” experiment (or use the PV1 control panel directly).
2. No-load measurement: Before connecting $R_L$, set PV1 to several voltages and record $V_{A1}$ each time. This establishes the open-circuit ($V_{OC}$) baseline — any deviation here is due to the input impedance of A1 ($1\text{ M}\Omega$), which is negligible.
3. Connect $R_L$: Connect the $100\text{ }\Omega$ load from PV1 to GND with A1 still monitoring PV1.
4. Sweep the set-point: Increase $V_{set}$ in steps from $0\text{ V}$ upward. At each step, record:
   • The programmed set-point voltage $V_{set}$
   • The actual terminal voltage $V_{terminal}$ read from A1
5. Continue until the terminal voltage clearly stops tracking the set-point (saturation / current limit is reached).
6. Plot $V_{terminal}$ vs $V_{set}$. The ideal curve is the $45°$ line $V_{terminal} = V_{set}$. Deviation from this line marks the onset of current limiting.
7. Calculate $Z_{out}$ in the linear region using the formula in §3.3 at a chosen operating point.

6. Observation Table

Load Resistor $R_L$: ____ $\Omega$

6a. No-Load ($R_L$ disconnected)

6b. Loaded ($R_L = 100\text{ }\Omega$ connected)

7. Results and Discussion

• In the no-load condition, $V_{terminal} \approx V_{set}$ across the full range, confirming that the input impedance of A1 has negligible loading effect.
• With $R_L = 100\text{ }\Omega$ connected, the terminal voltage tracked the set-point closely at low voltages but began to deviate at $V_{set} \approx$ ____ V, indicating the onset of current saturation.
• The output impedance $Z_{out}$ was estimated to be approximately ____ $\Omega$ from the loaded measurements in the linear region.
• The maximum current deliverable by PV1 before saturation was approximately $I_{max} = V_{terminal,\text{sat}} / R_L =$ ____ mA.
• The results demonstrate that a practical source behaves ideally only when the load current is well below its current limit, i.e., when $R_L \gg Z_{out}$.

8. Precautions

1. Do not short-circuit PV1: Never connect PV1 directly to GND without a load resistor. With $Z_{out}$ being small, even a short circuit draws a very large current that may damage the output stage. Always keep $R_L \geq 100\text{ }\Omega$.
2. Monitor A1, not the software set-point: The set-point displayed in the software is what the firmware requests; the actual output depends on the load. Always use the A1 reading as the true terminal voltage.
3. Allow settling time: After changing $V_{set}$, wait briefly for the output to settle before recording the A1 value, especially at higher currents where the internal regulator may take a moment to stabilize.
4. Component power rating: At $5\text{ V}$ across $100\text{ }\Omega$, the power dissipated is $P = V^2/R_L = 250\text{ mW}$. Ensure the resistor is rated for at least $0.5\text{ W}$ to avoid overheating.

9. Troubleshooting