Full-Wave Rectifier Using Two PN Junction Diodes

Experiment: Full-Wave Rectifier Using Two PN Junction Diodes

1. Aim

To construct a full-wave rectifier using two PN junction diodes with the SEELab3’s complementary outputs WG and $\overline{\textbf{WG}}$, to observe that both halves of the AC cycle are rectified, and to compare the output — with and without a filter capacitor — against the half-wave rectifier studied previously.

2. Apparatus / Components Required

• SEELab3 unit
• Two PN junction diodes (1N4148 or 1N4007)
• Load resistor $R_L = 1\text{ k}\Omega$
• Filter capacitor $C = 1\text{ }\mu F$
• Breadboard and connecting wires
• PC or Smartphone with SEELab3 software

3. Theory & Principle

A full-wave rectifier utilises both halves of the AC cycle, unlike a half-wave rectifier which discards the negative half. This requires two AC inputs that are $180°$ out of phase with each other — traditionally provided by the two ends of a centre-tapped transformer.

SEELab3 provides this directly through its two complementary wave generator outputs:

• WG — the primary sinusoidal output
• $\overline{\textbf{WG}}$ — the same signal inverted ($180°$ phase-shifted)

The two diodes operate in alternation:

• When WG is positive ($\overline{\text{WG}}$ negative) — D1 conducts, D2 blocks.
• When $\overline{\text{WG}}$ is positive (WG negative) — D2 conducts, D1 blocks.

In both cases current flows through $R_L$ in the same direction, so the output consists of rectified humps from every half-cycle.

The key improvements over half-wave rectification are summarised below:

Since the ripple frequency is $2f$, the capacitor discharges for only half the period before being recharged, giving much lower ripple for the same $RC$.

4. Circuit Diagram / Setup

1. Connect the anode of D1 to WG; connect the anode of D2 to $\overline{\textbf{WG}}$.
2. Connect the cathodes of both D1 and D2 together at a common node — this is the output node.
3. Connect $R_L$ from the output node to GND.
4. A1 monitors WG (input).
5. A2 monitors $\overline{\text{WG}}$ (inverted input).
6. A3 monitors the output node (across $R_L$).

For the filter stage, connect $C = 1\text{ }\mu F$ in parallel with $R_L$ after completing the unfiltered observations.

5. Procedure

1. Open the SEELab3 app and select the “Full-Wave Rectifier” experiment.
2. Set WG to a sinusoidal output at $f = 1000\text{ Hz}$, amplitude $\approx 3\text{ V}$ peak.
3. Click “Start”. Observe the three traces on A1, A2, and A3:
   • A1 and A2 should be identical sinusoids $180°$ apart.
   • A3 should show a full-wave rectified waveform — positive humps at twice the input frequency with no missing half-cycles.
4. Record the peak output voltage and confirm the $V_f$ drop ($\approx 0.6\text{ V}$) from the input peak.
5. Note the ripple frequency on A3 — it should be $2 \times 1000 = 2000\text{ Hz}$.
6. Add the filter capacitor ($1\text{ }\mu F$ in parallel with $R_L$). Observe A3 again — compare the ripple amplitude and average DC level with the unfiltered output and with the filtered half-wave result from the previous experiment.

6. Observation Table

6a. Unfiltered Output

6b. Filtered vs Unfiltered Comparison ($C = 1\text{ }\mu F$)

7. Results and Discussion

• The output at A3 showed rectified humps for both halves of the AC cycle, confirming full-wave rectification.
• The output peak was ____ V, a drop of ____ V from the input peak due to one diode forward voltage $V_f$.
• The ripple frequency was ____ Hz — twice the input frequency of 1000 Hz — consistent with both half-cycles contributing to the output.
• With $C = 1\text{ }\mu F$, the ripple reduced to ____ V peak-to-peak and the average DC output rose to ____ V.
• Compared to the filtered half-wave result (____ V ripple), the full-wave filter produces lower ripple for the same capacitor value, because the capacitor is recharged at twice the frequency and has less time to discharge between peaks.

8. Precautions

1. Diode polarity: Both cathodes must point toward the output node. A reversed diode will short one of the WG outputs to GND through a forward-biased junction.
2. $\overline{\text{WG}}$ availability: The complementary output $\overline{\text{WG}}$ is a feature of SEELab3. Verify your unit has this terminal before building the circuit.
3. A3 range: Ensure the output voltage stays within the safe input range of A3. With a 3 V input, the output peak ($\approx 2.4\text{ V}$) is well within range.
4. Capacitor polarity: Connect the positive terminal of the electrolytic capacitor to the output node (A3 side) and negative to GND.

9. Troubleshooting