Clamping Circuit Using a PN Junction Diode

Experiment: Clamping Circuit Using a PN Junction Diode

1. Aim

To study the action of a diode clamping circuit — a circuit that shifts the entire AC waveform up or down by adding a DC offset — and to observe how the clamped output level is controlled by the DC bias applied through PV1.

2. Apparatus / Components Required

• SEELab3 unit
• PN junction diode (1N4148)
• Capacitor $C = 1\text{ }\mu F$
• Connecting wires
• PC or Smartphone with SEELab3 software

3. Theory & Principle

3.1 Clipper vs Clamper — the key distinction

A clipper (previous experiment) cuts away part of the waveform — the shape of the surviving portion is unchanged but some of it is removed. A clamper shifts the entire waveform up or down without altering its shape — the peak-to-peak amplitude is preserved, only the DC level changes.

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3.2 How the clamper works

The circuit consists of a series capacitor $C$ between WG and the output node, with a diode connecting the output node to PV1.

On the first negative peak of the input, the output node is pulled low and the diode becomes forward biased, clamping the output node to:

The capacitor charges rapidly to the difference $V_{in,\text{neg_peak}} - V_{clamp}$ and holds this charge. On subsequent cycles the capacitor’s stored voltage acts as a DC offset, shifting the entire waveform upward so that the negative peaks sit at $V_{clamp}$.

For a $3\text{ V}$ peak sinusoid and $V_{PV1} = 1\text{ V}$:

The entire waveform is lifted so its lowest point sits at $\approx +0.3\text{ V}$, and the positive peak rises to $\approx 0.3 + 6 = 6.3\text{ V}$ (peak-to-peak preserved at $6\text{ V}$).

Important: The output peak-to-peak voltage equals the input peak-to-peak — the clamper adds DC offset only. This is what distinguishes it from a clipper, which reduces peak-to-peak.

3.3 Reverse clamping

Reversing the diode flips the action — the diode now clamps the positive peaks instead of the negative ones, shifting the entire waveform downward. Applying a negative voltage to PV1 with the reversed diode clamps the positive peaks below zero.

4. Circuit Diagram / Setup

1. Connect WG to one plate of capacitor $C$ ($1\text{ }\mu F$). Connect A1 to WG to monitor the input.
2. Connect the other plate of $C$ to the anode of the diode. This is the output node — connect it to A2.
3. Connect the cathode of the diode to PV1.

For reverse clamping: swap the diode (cathode to output node, anode to PV1) and apply negative voltages on PV1.

5. Procedure

Part A — Positive (upward) clamping

1. Open the SEELab3 app. Set WG to a sinusoidal output at $f = 1000\text{ Hz}$, amplitude $\approx 3\text{ V}$ peak.
2. Set PV1 = 1 V. Click “Start” and observe A1 and A2.
   • A1 shows the original symmetric sinusoid centred on $0\text{ V}$.
   • A2 should show the same waveform shifted upward — negative peaks lifted to $\approx V_{PV1} - 0.6\text{ V}$.
3. Confirm the peak-to-peak amplitude of A2 equals that of A1.
4. Vary PV1: 0 V, 0.5 V, 1.0 V, 1.5 V, 2.0 V. Record the clamped negative-peak level each time.

Part B — Reverse (downward) clamping

1. Reverse the diode and set PV1 to negative values: 0 V, −0.5 V, −1.0 V, −1.5 V.
2. Observe that the positive peaks are now clamped and the waveform shifts downward.
3. Record the clamped positive-peak level at each PV1 setting.

6. Observation Table

6a. Part A — Positive Clamping

6b. Part B — Reverse Clamping (diode reversed)

7. Results and Discussion

• With PV1 = 1 V, the negative peaks of the output were clamped to ____ V, against a theoretical value of $1.0 - 0.6 = 0.4\text{ V}$.
• The peak-to-peak amplitude at A2 was ____ V, equal to the input peak-to-peak of ____ V, confirming that the clamper preserves waveform shape and only shifts the DC level.
• As PV1 was increased, the clamped level rose proportionally — each $1\text{ V}$ increase in PV1 raised the output by $1\text{ V}$, verifying $V_{clamp} = V_{PV1} - V_f$.
• With the diode reversed and PV1 negative, the waveform shifted downward symmetrically, confirming that the clamping direction is controlled entirely by diode orientation and PV1 polarity.

8. Precautions

1. Capacitor value: The capacitor must fully charge within the first few cycles for steady-state clamping to be established. For $f = 1000\text{ Hz}$, $C = 1\text{ }\mu F$ with the $1\text{ M}\Omega$ input impedance of A2 gives $\tau = RC = 1\text{ s}$ — very long. In practice the diode provides a fast charge path on the clamping half-cycle; however, the discharge through $1\text{ M}\Omega$ is slow, which is what holds the DC shift. Do not add a low-value load resistor across the output — it will discharge the capacitor too quickly and degrade the clamping action.
2. A2 input impedance dependence: The clamped DC level depends on the $1\text{ M}\Omega$ input impedance of A2 holding the capacitor charge between cycles. With a real load (e.g., $10\text{ k}\Omega$) the clamping will degrade — the practical clamper needs a buffer amplifier for low-impedance loads.
3. Allow settling: The output takes a few cycles to settle to steady-state after changing PV1. Wait briefly before recording measurements.
4. Capacitor polarity: If an electrolytic capacitor is used, it must be oriented correctly. Preferred: use a non-polarised film or ceramic capacitor for this experiment.

9. Troubleshooting